Technical Field
This invention relates generally to the field of semiconductors, and more particularly, to approaches used in forming contacts in semiconductor devices.
Related Art
A typical integrated circuit (IC) chip includes a stack of several levels or sequentially formed layers of shapes. Each layer is stacked or overlaid on a prior layer and patterned to form the shapes that define devices (e.g., fin-type field effect transistors (FinFETs)) and connect the devices into circuits. In a typical state of the art complementary insulated gate FinFET process, such as what is normally referred to as CMOS, layers are formed on a wafer to form the devices on a surface of the wafer. Further, the surface may be the surface of a silicon layer on a silicon on insulator (SOI) wafer. A simple FinFET is formed by the intersection of two shapes, i.e., a gate layer rectangle on a silicon island formed from the silicon surface layer. Each of these layers of shapes, also known as mask levels or layers, may be created or printed optically through well-known photolithographic masking, developing and level definition, e.g., etching, implanting, deposition, etc.
For FinFET devices, it is typical to have a source/drain contact strap over an active region (Rx) to make sure all FINs are connected by contact. Prior art approaches consist of etching a contact hole in the contact strap layer (TS), or contact layer, and then filling the hole with a metal to contact source and drain. The shape of the contact plug is dictated by the shape of the hole, which is usually tapered, yet close to vertical. However, with the current tapered shape of contacts to source and drain, it becomes difficult to expect yield for a contact that allows contact resistance in specification, while avoiding bridging at the top of adjacent contacts.
Another issue with current art approaches is performing a uniform, repeatable contact to the S/D areas. With FinFET technology, a contact area typically encompasses a number of fins. Because of process variability and design rules constraints related to crowding at the top of the contacts, design becomes problematic at 14 nm and smaller because the fin located on the edge of the contact receives only partial coverage with the contact metal, thus resulting in an increased resistance.
In another prior art approach, middle of line (MOL) processing for 14 nm FinFET fully encapsulates the gate in nitride. A contact to S/D is etched through oxide, selectively to nitride (TS level). This contact is therefore self-aligned. After TS metallization and CMP, an Inter-Layer Dielectric (ILD) film is deposited, and the S/D contact to TS and gate contact are processed.
In yet another prior art approach, a replacement metal contact scheme is used for contact to S/D at 10XM dimensions because the requirements in terms of overlay for the S/D triple patterning are too stringent to expect yield otherwise. However, this prevents the processing of contact(s) to gate before the S/D contacts, as is the case with 14XM. Furthermore, this integration degrades the critical dimensions (CD) when stripping the dummy organic planarizing layer (OPL) filling the S/D contact cavity.